Biometric Systems and Their Applications

Nowadays, we are talking more and more about insecurity in various sectors as well as the computer techniques to be implemented to counter this trend: access control to computers, e-commerce, banking, etc. There are two traditional ways of identifying an individual. The first method is a knowledge-based method. It is based on the knowledge of an individual’s information such as the PIN code to allow him/her to activate a mobile phone. The second method is based on the possession of token. It can be a piece of identification, a key, a badge, etc. These two methods of identification can be used in a complementary way to obtain increased security like in bank cards. However, they each have their weaknesses. In the first case, the password can be forgotten or guessed by a third party. In the second case, the badge (or ID or key) may be lost or stolen. Biometric features are an alternative solution to the two previous identification modes. The advantage of using the biometric features is that they are all universal, measurable, unique, and permanent. The interest of applications using biometrics can be summed up in two classes: to facilitate the way of life and to avoid fraud

An energy-aware system-on-chip architecture for intra prediction in HEVC standard

High resolution 4K and 8K are becoming the more used in video applications. Those resolutions are well supported in the new HEVC standard. Thus, embedded solutions such as development of dedicated ystems-On-Chips (SOC) to accelerate video processing on one chip instead of only software solutions are commendable. This paper proposes a novel parallel and high efficient hardware accelerator for the intra prediction block. This accelerator achieves a high-speed treatment due to pipelined processing units and parallel shaped architecture. The complexity of memory access is also reduced thanks to the proposed design with less increased power consumption. The implementation was performed on the 7 Series FPGA 28 nm technology resources on Zynq-7000 and results show, that the proposed architecture takes 16520 LUTs and can reach 143.65 MHz as a maximum frequency and it is able to support the throughput of 3840×2160 sequence at 90 frames per second

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms.  In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF).  An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms

A Comparative Study of Multiple Object Detection Using Haar-Like Feature Selection and Local Binary Patterns in Several Platforms

Object detection has been attracting much interest due to the wide spectrum of applications that use it. It has been driven by an increasing processing power available in software and hardware platforms. In this work we present a developed application for multiple objects detection based on OpenCV libraries. The complexity-related aspects that were considered in the object detection using cascade classifier are described. Furthermore, we discuss the profiling and porting of the application into an embedded platform and compare the results with those obtained on traditional platforms. The proposed application deals with real-time systems implementation and the results give a metric able to select where the cases of object detection applications may be more complex and where it may be simpler

The conducted immunity of SPI EEPROM memories

International audienceThis paper focus on the conducted immunity measurement of non-volatile memories up to 1 GHz. A specific measurement flow is introduced, which makes possible to compare the EMC performances in different test cases. Trough measurements and simulation, this study gives a real view on the immunity difference of this integrated circuits (IC)

Analysis of HEVC Video Encoder Using ARM Cortex –A8 with NEON Technology

This work presents an implementation of the last software version of video processing the High Efficiency Video Coding (HEVC) encoder in architecture of mobile processors single low cost processor ARM Cortex A8 using on NEON architecture which is a Single Input Multiple Data (SIMD). By using an optimization using this technology the execution time was highly accelerated

On the ways of the HEVC/H265 standard

High Efficiency Video Coding (HEVC) is the new video compression standard developed by a Joint Collaborative Team of ISO/IEC MPEG and ITU-T VCEG. Standardized in January 2013, HEVC was designed to offer significantly improved compression performances relative to precedent standards by using several new tools for improving coding efficiency. This paper gives an overview of HEVC standard and makes a comparison between two implementations of the HM 12.0 reference software

Etude de structures MS et MIS-(n)InP par photoluminescence : effet du champ électrique

InP is an attractive III-V compound semiconductor for optoelectronics and high frequency devices, and for high-speed integrated circuits. That explains the extensive researches developed about this compound. In this work, measurements of the band-edge photoluminescence intensity under electrical field are used to characterize metal/semiconductor MS and metal/insulator/semiconductor MIS structures on n-InP. Schottky and oxidized Schottky diodes were studied. Comparison of measured characteristics of these two types of samples shows that the oxydation introduces surface or interface states. These defects can be responsible for at least a partiel pinnig of the surface Fermi level. In the case of oxidized Schottky diodes, using multipolar plasma, the photoluminescence measurements show that the schottky barrier height, deduced from the current-voltage characteristic, must be considered as an effective barrier. For MIS structures obtained by growing native oxide by a plasma bilayer technique, a detailed photoluminescence study in reserve bias region was performed and, by comparison of theoretical curves and experimental results, it is concluded that the surface recombinaison velocity is small. To describe the behaviour of the photoluminescence intensity in accumulation, a model is proposed and discussed. Finally a preliminary study of metal/BN/InP structures is presentedLe phosphure d'indium (InP) est un semiconducteur composé III-V très attractif pour des applications dans les domaines de l'optoélectronique, des hyperfréquences et aussi pour la fabrication de circuits intégrés rapides. Ceci explique l'intense activité de recherche qui s'est développée autour de ce composé. Le travail présenté dans ce mémoire concerne l'étude par photoluminescence, en présence d'un champ électrique, de structures métal/semiconducteur (MS) et métal/isolant/semiconducteur (MIS). Des diodes schottky et schottky oxydées ont été étudiées. la comparaison des caractéristiques de ces deux structures montre que l'oxydation s'accompagne de l'introduction d'états de surface ou d'interface. Ces défauts peuvent être à l'origine d'un blocage au moins partiel du niveau de fermi à la surface. En particulier, pour les structures oxydées dans un plasma multipolaire d'oxygène, les mesures de photoluminescence permettent de montrer que la hauteur de la barrière schottky déduite de la caractéristique courant-tension doit être considérée comme une barrière apparente. Sur des structures MIS ou l'isolant est un oxyde plasma Rf, une étude détaillée de l'intensité de photoluminescence en dépletion montre que la vitesse de recombinaison en surface est faible. Pour décrire l'évolution de l'intensité de photoluminescence Ip(Vg) en régime d'accumulation, un modèle est proposé et discuté. Enfin une étude préliminaire sur des structures métal/BN/InP est présenté

Accurate surface potential determination in Schottky diodes by the use of a correlated current and capacitance voltage measurements. Application to n-InP

Based on current voltage (I—Vg) and capacitance voltage (C—Vg) measurements, a reliable procedure is proposed to determine the effective surface potential Vd(Vg) in Schottky diodes. In the framework of thermionic emission, our analysis includes both the effect of the series resistance and the ideality factor, even voltage dependent. This technique is applied to n-type indium phosphide (n-InP) Schottky diodes with and without an interfacial layer and allows us to provide an interpretation of the observed peak on the C—Vg measurements. The study clearly shows that the depletion width and the flat band barrier height deduced from C—Vg, which are important parameters directly related to the surface potential in the semiconductor, should be estimated within our approach to obtain more reliable information

Bulk-driven current conveyor optimization using simulation-based method

This paper presents the optimization of a novel low-voltage (LV) and low-power (LP) bulk driven current conveyor (CCII). For the bulk-driven circuits, the transistors are biased at the subthreshold regime for LV and LP operation. In contrast, the input transistors of the differential stage are controlled from the bulk terminals to achieve a rail-to-rail input voltage range. A simulation-based technique is adapted for the optimal design of LV-LP bulk driven CCII, using the single-objective particle swarm optimization (PSO) algorithm. It is designed using CMOS 0.18 μm technology to operate at a voltage of 0.3 V and have a power consumption of 37 nW. Optimization results and also process/temperature corner results confirm the correct operation of the designed circuit